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| 2. |
- Herrholz, Andreas, et al.
(författare)
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The ANDRES Project : Analysis and Design of run-time Reconfigurable, heterogeneous Systems
- 2007
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Ingår i: Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. - : IEEE. - 9781424410606 - 1424410606 ; , s. 396-401
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Konferensbidrag (refereegranskat)abstract
- Today's heterogeneous embedded systems combine components from different domains, such as software, analogue hardware and digital hardware. The design and implementation of these systems is still a complex and error-prone task due to the different Models of Computations (MoCs), design languages and tools associated with each of the domains. Though making such systems adaptive is technologically feasible, most of the current design methodologies do not explicitely support adaptive architectures. This paper present the ANDRES project. The main objective of ANDRES is the development of a seamless design flow for adaptive heterogeneous embedded systems (AHES) based on the modelling language SystemC. Using domain-specific modelling extensions and libraries, ANDRES will provide means to efficiently use and exploit adaptivity in embedded system design. The design flow is completed by a methodology and tools for automatic hardware and software synthesis for adaptive architectures.
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| 3. |
- Jantsch, Axel, et al.
(författare)
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Models of computation and languages for embedded system design
- 2005
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Ingår i: IEE Proceedings - Computers and digital Techniques. - : Institution of Engineering and Technology (IET). - 1350-2387 .- 1359-7027. ; 152:2, s. 114-129
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Tidskriftsartikel (refereegranskat)abstract
- Models of computation (MoC) are reviewed and organised with respect to the time abstraction they use. Continuous time, discrete time, synchronous and untimed MoCs are distinguished. System level models serve a variety of objectives with partially contradicting requirements. Consequently, it is argued that different MoCs are necessary for the various tasks and phases in the design of an embedded system. Moreover, different MoCs have to be integrated to provide a coherent system modelling and analysis environment. The relation between some popular languages and the reviewed MoCs is discussed to find that a given MoC is offered by many languages and a single language can support multiple MoCs. It is contended that it is of importance for the quality of tools and overall design productivity, which abstraction levels and which primitive operators are provided in a language. However, it is observed that there are various flexible ways to do this, e.g. by way of heterogeneous frameworks, coordination languages and embedding of different MoCs in the same language.
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| 4. |
- Jantsch, Axel, et al.
(författare)
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Models of Computation in the Design Process
- 2006
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Ingår i: System-on-Chip. - : Institution of Engineering and Technology. - 9780863415524 ; , s. 161-185
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Bokkapitel (refereegranskat)
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| 5. |
- Lu, Zhonghai, et al.
(författare)
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Feasibility analysis of messages for on-chip networks using wormhole routing
- 2005
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Ingår i: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2. - New York, New York, USA : IEEE conference proceedings. ; , s. 960-964
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Konferensbidrag (refereegranskat)abstract
- The feasibility of a message in a network concerns if its timing property can be satisfied without jeopardizing any messages already in the network to meet their timing properties. We present a novel feasibility analysis for real-time (RT) and non-realtime (NT) messages in wormhole-routed networks on chip. For RT messages, we formulate a contention tree that captures contentions in the network. For coexisting RT and NT messages, we propose a simple bandwidth partitioning method that allows us to analyze their feasibility independently.
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| 6. |
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| 7. |
- Lu, Zhonghai, et al.
(författare)
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Refining synchronous communication onto network-on-chip best-effort services
- 2006
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Ingår i: Applications of Specification and Design Languages for SoCs. - DORDRECHT : Springer. - 1402049978 ; , s. 23-38
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Konferensbidrag (refereegranskat)abstract
- We present a novel approach to refine a system model specified with perfectly synchronous communication onto a network-on-chip (NoC) best-effort communication service. It is a top-down procedure with three steps, namely, channel refinement, process refinement, and communication mapping. In channel refinement, synchronous channels are replaced with stochastic channels abstracting the best-effort service. In process refinement, processes are refined in terms of interfaces and synchronization properties. Particularly, we use synchronizers to maintain local synchronization of processes and thus achieve synchronization consistency, which is a key requirement while mapping a synchronous model onto an asynchronous architecture. Within communication mapping, the refined processes and channels are mapped to an NoC architecture. Adopting the Nostrum NoC platform as target architecture, we use a digital equalizer as a tutorial example to illustrate the feasibility of our concepts.
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| 8. |
- Lu, Zhonghai, et al.
(författare)
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Towards performance-oriented pattern-based refinement of synchronous models onto NoC communication
- 2006
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Ingår i: DSD 2006: 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, Proceedings. - 0769526098 ; , s. 37-44
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Konferensbidrag (refereegranskat)abstract
- We present a performance-oriented refinement approach that refines a perfectly synchronous communication model onto Network-on-Chip (NoC) communication. We first identify four basic forms of NoC process interaction patterns at the process level, namely, producer-consumer, peers, client-server and multicast. We propose a three-step top-down refinement method: channel refinement, protocol refinement and channel mapping. For the producer-consumer pattern, we describe it in detail. In channel refinement, we deal with interfacing multiple clock domains and use a stochastic process to model channel delay and jitter In protocol refinement, we show how to refine communication towards application requirements such as reliability and throughput. In channel mapping, we discuss channel convergence and channel merge arising from channel overlapping. All the refinements have been conducted and validated as an integral design phase towards implementation in ForSyDe, a formal system-level design methodology based on a synchronous model of computation.
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| 9. |
- Lu, Zhonghai, et al.
(författare)
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Using synchronizers for refining synchronous communication onto Hardware/Software architectures
- 2007
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Ingår i: RSP 2007. - : IEEE Computer Society. - 9780769528342 ; , s. 143-149
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Konferensbidrag (refereegranskat)abstract
- We have presented a formal set of synchronization components called synchronizers for refining synchronous communication onto HW/SW codesign architectures. Such an architecture imposes asynchronous communication between HW-HW SW-SW and HW-SW components. The synchronizers enable local synchronization, thus satisfy the synchronization requirement of a typical IP core. In this paper we present their implementations in HW, SW and HW/SW as well as their application. To validate our concepts, we conduct a case study on a Nios FPGA that comprises a processor memory and custom logic. The final HW/SW implementation achieves equivalent performance to pure HW implementation. Our prototyping experience suggests that the synchronizers can be standardized as library modules and effectively separate the design of computation from that of communication.
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| 10. |
- Raudvere, Tarvo, et al.
(författare)
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A Synchronization Algorithm for Local Temporal Refinements in Perfectly Synchronous Models with Nested Feedback Loops
- 2007
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Ingår i: GLSVLSI'07. - NEW YORK : ASSOC COMPUTING MACHINERY. - 9781595936059 ; , s. 353-358
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Konferensbidrag (refereegranskat)abstract
- Due to the abstract and simple computation and communication mechanism in the synchronous computational model it is easy to simulate synchronous systems and to apply formal verification methods. In synchronous models, a local temporal refinement that increases the delay in a single computation block may affect the functionality of the entire model. To preserve the system's functionality after temporal refinements we provide a synchronization algorithm that applies also to models with nested feedback loops. The algorithm adds pure delay elements to the model in order to balance the delay caused by refinement and to assure concurrent data arrival at computation blocks. It is done so that the refined model stays latency equivalent to the original model. The advantages of our approach are that (a) we remain fully within the synchronous model of computation, (b) we preserve the functionality of the existing computation blocks, and (c) we do not require additional computation resources, wrapper circuits or schedulers.
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